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IS82C600 integrated silicon solution, inc. 1-800-379-4774 1 preliminary tb001-0b 01/20/99 issi ? this document contains preliminary data. issi reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 1999, integrated silicon solution, inc. trailblazer high-speed sram with address decoding and ready logic features ? zero wait-state performance on the primary bus point-to-point interface between the sram and the high-speed processor ? seamless interface to texas instruments tms320lc54x high-speed processor ? integrates the single-ported sram with a dual- ported interface and handshake 9 ns access time to the sram can also be used as a standalone, high- speed sram ? integrates the port-to-port bridge function broadcasts all processor cycles from primary bus to the secondary bus programmability to only broadcast non-sram cycles to the secondary bus supports older, slower peripheral devices on the secondary bus allows the processor transparent access to the devices on the secondary bus through xcvr pin supports a boot rom on the secondary bus general description the IS82C600 trailblazer simplifies high-speed system design and layout, providing an sram with zero wait-state performance up to 90 mhz, address coding, and ready logic. in many cases, trailblazer allows existing system designs to be easily upgraded, enabling the re-use of already available asics and glue logic. a key benefit of the trailblazer device is its ability to relieve high-performance processors from a necessity to drive heavily loaded multidrop buses by providing a point-to- ? features address decoding and ready logic a total of six chip selects supports ready logic signal generation for memory and i/o eliminates pals for address decoding and ready logic no glue logic interface for local peripherals on the secondary bus processor ? allows dynamic re-allocation of memory spaces for transparent block moves programmable memory decoding allows memory blocks to be accessed as either program space ( ps ) or data space ( ds ) programmable registers to map the internal sram memory and external secondary port devices into data space ( ds ), program space ( ps ) and i/o space ( is ) ? can also be used as a standalone, high-speed sram ? allows the shadowing of the rom on the secondary bus into the on-board sram IS82C600 point, low-load interconnect to the high-speed memory and buffering of the slower speed devices. this could allow the processors to operate at a maximum frequency with zero wait-states. also, it eases pcb timing and layout- related considerations, often allowing a reduction in the number of pc board layers and the lowering of noise. programmable decodes and "ready" generation logic built into the trailblazer eliminates the need for expensive pals, other glue logic, and additional board space. preliminary january 1999 issi ?
2 integrated silicon solution, inc. 1-800-379-4774 preliminary tb001-0b 01/20/99 IS82C600 issi ? figure 1. trailblazer functional block diagram product overview the IS82C600 trailblazer integrates a high-speed 64k x 16 sram with a processor port-to-processor port bridge function. this simplifies any high-speed designs by providing a fast access time for the processor on the primary port and enabling for a low-cost implementation of a high-frequency system. trailblazer combines a high-performance memory array, programmable decodes, and "ready" logic to achieve maximum performance and flexibility, while keeping costs at a minimum. in order to simplify system development, trailblazer duplicates the primary bus signals on its secondary bus to permit the use of existing system components and asics together with a new generation of high-performance processors. on its primary bus, the trailblazer provides a high-speed sram interface and then broadcasts the primary bus cycles to its secondary bus, allowing the processor on its primary bus to access peripherals on its secondary bus. in many cases, since the peripherals are accessed by the same signals, existing asics can be re-used. trailblazer provides an optimized, seamless interface to ti tms320lc54x high-speed processor without the need for any glue logic interfaces for local peripherals on the secondary bus. trailblazer can also be used as shared local or global memory for a dual processor-based system where the chip select logic on each bus allows for the same data to be accessed at different locations in memory, if so desired. decoder sram 64k x 16 bus repeater psp dsp isp r/wp holdap iostrbp mstrbp dp[15:0] ap[15:0] ds[15:0] as[15:0] csintp ap[21:16] rdy clk prgm xcvr csints csmems[5:0] wemems oemems pss dss iss r/ws holdas iostrbs mstrbs psp dsp isp r/wp holdap iostrbp mstrbp wes pss dss iss r/ws holdas iostrbs mstrbs
IS82C600 integrated silicon solution, inc. 1-800-379-4774 3 preliminary tb001-0b 01/20/99 issi ? figure 2. trailblazer system block diagram with high-speed dsp on the primary bus and the slower existing dsp system components on the secondary bus dsp csmems[0] trailblazer IS82C600 local device 1 local device 2 32k x 16 32k x 16 (register 0) (default) (register 5) (register 4) (register 3) (register 2) (register 1) local device 3 local device 4 local device 5 local device 6 csmems[1] as[15:0] ap[21:0] dp[15:0] r/w, strb ds[15:0] csmems[2] csmems[3] csmems[4] csmems[5] wemems
4 integrated silicon solution, inc. 1-800-379-4774 preliminary tb001-0b 01/20/99 IS82C600 issi ? pin information complete pin information on the device is organized as follows: ? overview ? conventions ? pin diagram ? pin assignment tablearranged by pin number ? pin assignment tablearranged by ball location ? detailed pin descriptions overview the r/ w signal determines the direction of the bus transaction. some processors, including ti tms320lc54x, have three major memory spaces. program space ( ps ); data space ( ds ); and i/o space ( is ). the memory space signals ( ds , ps , and is ) select the memory address space being accessed (data, program, or i/o). no more than one of the memory space signals can be asserted at the same time. data or program spaces (or any part of these spaces) can be mapped into either internal sram of the trailblazer or any external devices. i/o space can only be mapped to external devices. the trailblazers internal sram has two 32kb regions that are restricted to either ds or ps space. register 0 controls the decoding for the internal sram. registers 1 through 5 control the address decoding for the external devices on the secondary bus. for processors that have a15 as the msb, the three memory spaces are restricted to 64kb each. however, the registers do allow for programmable address ranges in 8kb blocks. for processors with a[21:16] as the msb, there is a 4mb maximum address space that can be partitioned by programming registers 1 to 5. chip selects ( csmem x) are used to select external devices on the secondary bus. these signals are generated by combinations of the memory space signals and addresses ap[13:21]. strobes ( mstrb and iostrb ) validate memory space selections. ps and ds have to be validated by the assertion of mstrb and is has to be validated by the assertion of iostrb . the following provides detailed technical information related to the pins on the device. for ease of reference, the pin information is presented in a table format arranged both by pin numbers and by pin names. a pin diagram has also been included to be used as a visual point of reference. conventions table 1 details conventions that are used to present information on the pins. table 1. pin conventions convention meaning nc this pin is reserved for issi, inc. and must be left as a 'no connect' i input-only o output-only i/o input or output (bi-directional) power power pin ground ground pin signal active (or asserted) state occurs when pin is at a low voltage / multiplexed or dual functionality pin diagram refer to figure 3 and table 2 for the pin diagram for the trailblazer device. it depicts the pin names and the corresponding ball location. pins marked as 'nc' are not available and are defined as 'no connect' pins. for more detailed information on the pins refer to table 5.
IS82C600 integrated silicon solution, inc. 1-800-379-4774 5 preliminary tb001-0b 01/20/99 issi ? figure 3. trailblazer pin diagram 7654 bottom view 32 1 a b c d e f g h j k l m n p r t u table 2. pin configuration: 119-pin pbga 1234567 a ap18 ap16 ap4 ap5 ap11 xcvr isp b ap19 ap17 ap3 ap6 ap12 psp dsp c ap21 ap20 ap2 ap7 ap13 dp0 dp1 d ds1 ds0 ap1 ap8 ap14 dp2 dp3 e ds3 ds2 ap0 ap9 ap15 dp4 dp5 f ds4 gnd gnd q ap10 gnd q v cc dp6 g ds7 ds6 ds5 dp7 holdap csintp r/ w p h clk gnd q rdy v ccq rdp gnd q iostrbp j ds8 oemems v ccq v ccq wes wep mstrbp k ds9 gnd q wemems v ccq iostrbs gnd q mstrbs l ds10 ds11 as1 as7 csints r/ w s rds m ds12 vcc gnd q as8 gnd q gnd holdas n ds13 ds14 as2 as9 dp10 dp9 dp8 p ds15 csmems0 as3 as10 dp13 dp12 dp11 r csmems1 csmems2 as4 as11 prgm dss dp14 t csmems3 csmems5 as5 as12 as15 iss dp15 u csmems4 as0 as6 as13 as14 pss nc
6 integrated silicon solution, inc. 1-800-379-4774 preliminary tb001-0b 01/20/99 IS82C600 issi ? table 3. pin assignment tablearranged by pin name in alphabetical order pin name ball location pin type ap0 e3 i/o ap1 d3 i/o ap2 c3 i/o ap3 b3 i/o ap4 a3 i/o ap5 a4 i/o ap6 b4 i/o ap7 c4 i/o ap8 d4 i/o ap9 e4 i/o ap10 f4 i/o ap11 a5 i/o ap12 b5 i/o ap13 c5 i/o ap14 d5 i/o ap15 e5 i/o ap16 a2 i ap17 b2 i ap18 a1 i ap19 b1 i ap20 c2 i ap21 c1 i as0 u2 i/o as1 l3 i/o as2 n3 i/o as3 p3 i/o as4 r3 i/o as5 t3 i/o as6 u3 i/o as7 l4 i/o as8 m4 i/o as9 n4 i/o as10 p4 i/o as11 r4 i/o as12 t4 i/o as13 u4 i/o as14 u5 i/o as15 t5 i/o clk h1 i csintp g6 i pin name ball location pin type csints l5 i csmems0 p2 o csmems1 r1 o csmems2 r2 o csmems3 t1 o csmems4 u1 o csmems5 t2 o dp0 c6 i/o dp1 c7 i/o dp2 d6 i/o dp3 d7 i/o dp4 e6 i/o dp5 e7 i/o dp6 f7 i/o dp7 g4 i/o dp8 n7 i/o dp9 n6 i/o dp10 n5 i/o dp11 p7 i/o dp12 p6 i/o dp13 p5 i/o dp14 r7 i/o dp15 t7 i/o ds0 d2 i/o ds1 d1 i/o ds2 e2 i/o ds3 e1 i/o ds4 f1 i/o ds5 g3 i/o ds6 g2 i/o ds7 g1 i/o ds8 j1 i/o ds9 k1 i/o ds10 l1 i/o ds11 l2 i/o ds12 m1 i/o ds13 n1 i/o ds14 n2 i/o ds15 p1 i/o dsp b7 i/o
IS82C600 integrated silicon solution, inc. 1-800-379-4774 7 preliminary tb001-0b 01/20/99 issi ? table 3. pin assignment tablearranged by pin name in alphabetical order (continued) pin name ball location pin type dss r6 i/o gnd f2 ground gnd m6 ground gnd q f3 ground gnd q f5 ground gnd q h2 ground gnd q h6 ground gnd q k2 ground gnd q k6 ground gnd q m3 ground gnd q m5 ground holdap g5 i holdas m7 i iostrbp h7 i/o iostrbs k5 i/o isp a7 i/o iss t6 i/o mstrbp j7 i/o mstrbs k7 i/o nc u7 oemems j2 o prgm r5 i psp b6 i/o pss u6 i/o rdp h5 i/o rds l7 i/o r/ w p g7 i/o r/ w s l6 i/o rdy h3 o v cc f6 power v cc m2 power v ccq h4 power v ccq j3 power v ccq j4 power v ccq k4 power wemems k3 o wep j6 i/o wes j5 i/o xcvr a6 i table 4. pin assignment tablearranged by ball location in alphabeltical order pin name ball location pin type ap18 a1 i ap16 a2 i ap4 a3 i/o ap5 a4 i/o ap11 a5 i/o xcvr a6 i isp a7 i/o ap19 b1 i ap17 b2 i ap3 b3 i/o ap6 b4 i/o ap12 b5 i/o psp b6 i/o dsp b7 i/o ap21 c1 i ap20 c2 i ap2 c3 i/o ap7 c4 i/o ap13 c5 i/o dp0 c6 i/o dp1 c7 i/o ds1 d1 i/o ds0 d2 i/o ap1 d3 i/o ap8 d4 i/o ap14 d5 i/o dp2 d6 i/o dp3 d7 i/o ds3 e1 i/o ds2 e2 i/o ap0 e3 i/o ap9 e4 i/o ap15 e5 i/o dp4 e6 i/o dp5 e7 i/o ds4 f1 i/o gnd f2 ground gnd q f3 ground ap10 f4 i/o
8 integrated silicon solution, inc. 1-800-379-4774 preliminary tb001-0b 01/20/99 IS82C600 issi ? table 4. pin assignment tablearranged by ball location in alphabeltical order (continued) pin name ball location pin type gnd q f5 ground v cc f6 power dp6 f7 i/o ds7 g1 i/o ds6 g2 i/o ds5 g3 i/o dp7 g4 i/o holdap g5 i csintp g6 i r/ w p g7 i/o clk h1 i gnd q h2 ground rdy h3 o v ccq h4 power rdp h5 i/o gnd q h6 ground iostrbp h7 i/o ds8 j1 i/o oemems j2 o v ccq j3 power v ccq j4 power wes j5 i/o wep j6 i/o mstrbp j7 i/o ds9 k1 i/o gnd q k2 ground wemems k3 o v ccq k4 power iostrbs k5 i/o gnd q k6 ground mstrbs k7 i/o ds10 l1 i/o ds11 l2 i/o as1 l3 i/o as7 l4 i/o csints l5 i r/ w s l6 i/o rds l7 i/o ds12 m1 i/o v cc m2 power pin name ball location pin type gnd q m3 ground as8 m4 i/o gnd q m5 ground gnd m6 ground holdas m7 i ds13 n1 i/o ds14 n2 i/o as2 n3 i/o as9 n4 i/o dp10 n5 i/o dp9 n6 i/o dp8 n7 i/o ds15 p1 i/o csmems0 p2 o as3 p3 i/o as10 p4 i/o dp13 p5 i/o dp12 p6 i/o dp11 p7 i/o csmems1 r1 o csmems2 r2 o as4 r3 i/o as11 r4 i/o prgm r5 i dss r6 i/o dp14 r7 i/o csmems3 t1 o csmems5 t2 o as5 t3 i/o as12 t4 i/o as15 t5 i/o iss t6 i/o dp15 t7 i/o csmems4 u1 o as0 u2 i/o as6 u3 i/o as13 u4 i/o as14 u5 i/o pss u6 i/o nc u7
IS82C600 integrated silicon solution, inc. 1-800-379-4774 9 preliminary tb001-0b 01/20/99 issi ? table 5. primary bus pins pin name pin type pin description ap[15:0] i/o address: primary bus address pins. the ap[21] is the msb and ap[0] is the lsb. ap[21:16] i clk i clock signal (primary): this is the high-speed clock from the processor. used for generation of rdy signal. csintp i internal sram chip select signal (primary): when asserted, the sram access is guaranteed from the primary bus, irrespective of the configuration mode. dp[15:0] i/o data: data pins dp[15] (msb) through dp[0] (lsb) connected to the processor on the primary bus. dsp i/o data space signal (primary): when asserted, indicates processor is accessing the data space ( ds ) memory. it also validates address information on ap[21:0]. holdap i hold acknowledge signal (primary): holdap , when asserted, indicates that the processor or mpu on the primary bus is in a hold state. this also indicates that ap[21:0] and dp[15:0] are tri-stated. typically, this signal is used in dual-processor configurations where access to the internal sram is guaranteed for the processor on the secondary bus. iostrbp i/o i/o strobe (primary): when asserted, indicates a primary bus access to i/o devices. isp i/o i/o space signal (primary): when asserted, indicates that processor is accessing the i/o space ( is ). it also validates the address. mstrbp i/o memory strobe (primary): when asserted, indicates bus access to data or program memory. psp i/o program space signal (primary): when asserted, indicates processor is communicating with program space ( ps ) memory. it also validates the address. rdp i/o this pin should be pulled high. r/ w p i/o read/write signal (primary): r/ w indicates transfer direction during access from primary bus. set high for a read and low for a write access. wep i/o this pin should be pulled high.
10 integrated silicon solution, inc. 1-800-379-4774 preliminary tb001-0b 01/20/99 IS82C600 issi ? table 6. secondary bus pins pin name pin type pin description as[15:0] i/o address: secondary bus address pins. as[15] is the msb and as[0] is the lsb. csints i internal sram chip select signal (secondary): when asserted, the sram access is guaranteed from the secondary bus (if holdap = 0), irrespective of the configuration mode. csmems[5:0] o external memory chip selects (secondary): selects devices on the secondary bus. refer to the register definition section for more details. dss i/o data space signal (secondary): when asserted, indicates processor is accessing the data space ( ds ) memory. it also validates address information on as[15:0]. holda si hold acknowledge signal (secondary): holda s, when asserted, indicates that the processor or mpu on the secondary bus is in a hold state. this also indicates that as[15:0] and ds[15:0] are tri-stated. typically, this signal is used in dual-processor configurations where access to the internal sram is guaranteed for the processor on the secondary bus. iostrbs i/o i/o strobe (secondary): when asserted, indicates a secondary bus access to i/o devices. iss i/o i/o space signal (secondary): when asserted, indicates that processor is accessing the i/o space ( is ). it also validates the address. mstrbs i/o memory strobe (secondary): when asserted, indicates bus access to data or program memory. pss i/o program space signal (secondary): when asserted, indicates processor is communicating with program space ( ps ) memory. it also validates the address. rds i/o this pin should be pulled high. r/ w s i/o read/write signal (secondary): r/ w indicates transfer direction during access from secondary bus. set high for a read access and low for a write access. wes i/o this should be pulled high. wemems o external memory write enable: this is the memory write enable signal for external memory or peripherals on the secondary bus. table 7. miscellaneous pins pin name pin type pin description prgm i program enable: this signal latches the secondary address bus, as[15:0], on its rising edge. typically, the prgm is derived from reset so that upon power-up, the state of as[15:0] is latched. as[15:8] determine the mode of internal sram decode and external memory decoding for the secondary bus. (see register descriptions for more detail.) rdy o rdy is asserted whenever a secondary bus device is able to communicate with the trailblazer. rdy is programmed in register 6 for various ds , is , and ps memory address spaces. xcvr i transceiver mode: this pin puts the trailblazer into a transceiver-like mode to support the processor's dma through the trailblazer, e.g., when a primary bus wants to read the data on the secondary bus. in this mode, the xcvr is asserted, and the holdas pin must be low, indicating no processors are on the secondary bus and the primary bus processor can read from the peripheral (or memory) from the secondary bus. (see table 8, bus logic truth table for every possible combination.) v ccq power power pins for i/o buffers of trailblazer. gnd q ground ground pins for i/o buffers of trailblazer. v cc power power pins for core of trailblazer. gnd ground ground pins for core of trailblazer note: 1. typically, v cc and v ccq are at 3.3 volts.
IS82C600 integrated silicon solution, inc. 1-800-379-4774 11 preliminary tb001-0b 01/20/99 issi ? table 8. bus logic truth table xcvr xcvr xcvr xcvr xcvr holda holda holda holda holda p holda holda holda holda holda s csint csint csint csint csint p csint csint csint csint csint s action csmem csmem csmem csmem csmem s[5:0] 0 0 x x x transceiver r/ w of csmem s[5:0] primary bus by are not asserted. secondary bus (dma). . 0 1 x x x transceiver r/ w of csmem s[5:0] secondary bus by are not asserted. primary bus (dma). 10 x x 0 r/ w of internal sram by csmem s[5:0] the secondary bus only. are not asserted 11 0 0 x r/ w of internal sram by csmem s[5:0] the primary bus only. are not asserted 1 1 0 1 x primary bus is in one of csmem s[5:0] control. r/ w from asserted, depending on external or internal ap[21:13] and ps p, memory by primary ds p and is p. bus. control signals are forward to the secondary bus. 11 1 0 x r/ w of internal sram by csmem s[5:0] the primary bus only. are not asserted control signals are not forwarded to the secondary bus. secondary bus access to internal memory denied. 11 1 1 x r/ w of internal csmem s[5:0] sram by primary are not asserted bus. control signals internal sram are not forwarded selection is based on to the secondary bus. ap[21:13], ps p and ds p secondary bus access to internal memory denied. figure 4. trailblazer interface with tms320lc54x dsp. trailblazer IS82C600 64k x 16 sram holdas csintp rdp wep r/wp mstrbp iostrbp hold csint r/w mstrb iostrb vcc vcc holdap a[15:0] d[15:0]
12 integrated silicon solution, inc. 1-800-379-4774 preliminary tb001-0b 01/20/99 IS82C600 issi ? register definitions a set of i/o addresses is reserved in the system and is used for trailblazer registers. as[15:8], when sampled by the rising edge of prgm , determine the displacement of the starting address for the registers from location 00. a block of 256 addresses from the starting address is not available for the system. for example, if as[15:8] are sampled as 80 (i.e., as[15] pulled high and as[14:8] pulled low) the starting i/o address is 8000h and i/o address 8000h to( 80+255)h are reserved. register 0 of trailblazer maps to 80 and register 1 maps to 81, and so on. currently, eight registers are defined and the remaining registers are reserved. all these registers will come up in their predetermined default states during power-up. upon power-up, the mode registers are loaded by sampling the as[15:0] (secondary address bus). these bits are sampled on the rising edge of the prgm . the prgm pin can be controlled in several different ways. the simpliest method is to tie the pin to the reset pulse of the processor. when prgm is asserted, the entire chip will be tri-stated and, therefore, normal functionality cannot be maintained while this pin is active. if the system requires a dynamic decoding of the address bits, the xf pin from the processor can be used as a gate to the decoding latch. register 0 trailblazer sram decode register (default ffff) this register is used to set the base address for each of the two 32k x 16 blocks of trailblazer sram. register 0 bits 6:0 are used for setting the starting address of a 32k block of sram and bit 7 determines if this block corresponds for ps or ds . when the ds / ps bit is 0, the block is in ds space and if 1, the block is in ps space. similarly, bits 15:8 programs the other 32k block. 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ds ds ds ds ds / ps ps ps ps ps a21 a20 a19 a18 a17 a16 a15 ds ds ds ds ds / ps ps ps ps ps a21 a20 a19 a18 a17 a16 a15 register 1 csmems0 csmems0 csmems0 csmems0 csmems0 pin select register (default 0008) this register is used to select the decoding for csmem s0. the decoding is on an 8k boundary and can be programmed to respond to ps , ds , or is address space or a combination thereof. the csmem s0 can be used as a chip select pin for external memory or i/o device. register 1 bits d[14:6] are used to set the base address for which the decode occurs, bits 5:3 determine the space, ps , ds , or is , and bits 2:0 determine the size of the decode. bit 15 is a reserved bit. on power-up, the register will reset at the default state of 0008. 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 rsvd a21 a20 a19 a18 a17 a16 a15 a14 a13 ps ps ps ps ps ds ds ds ds ds is is is is is sz2 sz1 sz0 bits 14 to 6 correspond to address bits a21 to a13 and sets the starting address for which csmem s0 is active. bits 5 to 3 determine the space for which the pin will be active which are encoded as follows: bits 2 to 0 determine the size for which csmem s0 will be active starting from address as determined by bits 14 to 6. rsrvd bit should always be programmed to zero.
IS82C600 integrated silicon solution, inc. 1-800-379-4774 13 preliminary tb001-0b 01/20/99 issi ? ps ps ps ps ps ds ds ds ds ds is is is is is space for which csmems0 csmems0 csmems0 csmems0 csmems0 will be active 000 csmems0 will not respond to any space, i.e., disabled. 001 csmems0 will be asserted for i/o space (when is asserted) as determined by the starting address and size bits. 010 csmems0 will be asserted for data space (when ds asserted) as determined by the starting address and size bits. 011 csmems0 will be asserted for i/o or data space (when is or ds asserted) as determined by the starting address and size bits. 100 csmems0 will be asserted for program space (when ps asserted) as determined by the starting address and size bits. 101 csmems0 will be asserted for program or i/o space (when ps or is asserted) as determined by the starting address and size bits. 110 csmems0 will be asserted for program or data space (when ps or ds asserted) as determined by the starting address and size bits. 111 csmems0 will be asserted for any space as determined by the starting address and size bits. size for which csmems0 csmems0 csmems0 csmems0 csmems0 will be active starting from the programmed starting sz2 sz1 sz0 address. the sizes are in the increments of 8k words. 00 0 csmems0 will be asserted for starting address to starting address + 8k 00 1 csmems0 will be asserted for starting address to starting address + 16k 01 0 csmems0 will be asserted for starting address to starting address + 32k 01 1 csmems0 will be asserted for starting address to starting address + 64k 10 0 csmems0 will be asserted for starting address to starting address + 128k 10 1 csmems0 will be asserted for starting address to starting address + 256k 11 0 csmems0 will be asserted for starting address to starting address + 512k 11 1 csmems0 will be asserted for starting address to starting address + 1024k register 2 csmems1 csmems1 csmems1 csmems1 csmems1 pin select register (default 0048): this register is used to select the decoding for csmem s1. the decoding is on an 8k boundary and can be programmed to respond to ps , ds , or is address space or a combination thereof. the csmem s0 can be used as chip select pin for external memory or i/o device. the bit descriptions and programmability are identical to register 1, except that the default is 0048. refer to csmem s0 bit descriptions. 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 rsvd a21 a20 a19 a18 a17 a16 a15 a14 a13 ps ps ps ps ps ds ds ds ds ds is is is is is sz2 sz1 sz0
14 integrated silicon solution, inc. 1-800-379-4774 preliminary tb001-0b 01/20/99 IS82C600 issi ? register 3 csmems2 csmems2 csmems2 csmems2 csmems2 pin select register (default 0088): this register is used to select the decoding for csmem s2. the decoding is on an 8k boundary and can be programmed to respond to ps , ds , or is address space or a combination thereof. the csmem s2 can be used as a chip select pin for external memory or i/o device. the bit descriptions and programmability are identical to register 1, except that the default is 0088. refer to csmem s0 bit descriptions. 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 rsvd a21 a20 a19 a18 a17 a16 a15 a14 a13 ps ps ps ps ps ds ds ds ds ds is is is is is sz2 sz1 sz0 register 4 csmems3 csmems3 csmems3 csmems3 csmems3 pin select register (default 00c8): this register is used to select the decoding for csmem s3. the decoding is on an 8k boundary and can be programmed to respond to ps , ds , or is address space or a combination thereof. the csmem s3 can be used as a chip select pin for external memory or i/o device the bit descriptions and programmability are identical to register 1, except that the default is 00c8. refer to csmem s0 bit descriptions. 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 rsvd a21 a20 a19 a18 a17 a16 a15 a14 a13 ps ps ps ps ps ds ds ds ds ds is is is is is sz2 sz1 sz0
IS82C600 integrated silicon solution, inc. 1-800-379-4774 15 preliminary tb001-0b 01/20/99 issi ? register 5 csmems4 csmems4 csmems4 csmems4 csmems4 pin select register (default 0112): this register is used to select the decoding for csmem s4. the decoding is on an 8k boundary and can be programmed to respond to ds or is address space or a combination thereof. the csmem s4 can be used as a chip select pin for external memory or i/o device. the bit descriptions and programmability are identical to register 1, except that the default is 0112. refer to csmem s0 bit descriptions. 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 rsvd rsvd rsvd rsvd rsvd rsvd rsvd a15 a14 a13 rsvd ds ds ds ds ds is is is is is rsvd sz1 sz0 ds ds ds ds ds is is is is is space for which csmems4 csmems4 csmems4 csmems4 csmems4 will be active 00 csmems0 will not respond to any space, i.e., disabled. 01 csmems0 will go active for i/o space (when is is active) as determined by the starting address and size bits. 10 csmems0 will go active for data space (when ds is active) as determined by the starting address and size bits. 11 csmems0 will go active for i/o or data space (when is or ds is active) as determined by the starting address and size bits. size for which csmems4 csmems4 csmems4 csmems4 csmems4 will be active starting from the programmed starting sz1 sz0 address. the sizes are in the increments of 8k words. 00 csmems0 will be active for starting address to starting address + 8k 01 csmems0 will be active for starting address to starting address + 16k 10 csmems0 will be active for starting address to starting address + 32k 11 csmems0 will be active for starting address to starting address + 64k csmems5 csmems5 csmems5 csmems5 csmems5 pin select register this is a negative decode of the other chip selects, i.e., it is active when csmem s[4:0] are high. \
16 integrated silicon solution, inc. 1-800-379-4774 preliminary tb001-0b 01/20/99 IS82C600 issi ? register 6 rdy generation logic and write control register (default ffff): register 6 is the signal rdy generation register for ps , ds , and is space. ps [4:0] (bits 4:0) determine the number of clocks after which the rdy is generated whenever ps goes active. similarly, ds [4:0] are used to program the rdy generation in number of clocks when ds is active and is [4:0] are used to generate the rdy for i/o cycles. the rdy signal could be used to delay an access to an external device on the secondary bus. please note that if an external rdy has to be sampled by the processor, the processors access should be programmed for at least two wait states. 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 we we we we we is4 is3 is2 is1 is0 ds4 ds3 ds2 ds1 ds0 ps4 ps3 ps2 ps1 ps0 notes: 1. the above registers are read/writable. 2. no csmems will be active if the i/o address of the registers matches with any csmems decodes. table 9. register accessibility register number register address register compare data chip select 0 ap[15:8] = sa ap[21:15]; ds p; ps p internal sram 1 ap[15:8] = sa+1 ap[21:13]; ds p; ps p; isp csmem s0 2 ap[15:8] = sa+2 ap[21:13]; ds p; ps p; is p csmem s1 3 ap[15:8] = sa+3 ap[21:13]; ds p; ps p; is p csmem s2 4 ap[15:8] = sa+4 ap[21:13]; ds p; ps p; is p csmem s3 5 ap[15:8] = sa+5 ap[15:13]; ds p; is p csmem s4 6 ap[15:8] = sa+6 ds p; ps p; is p csmem s5 notes: 1. sa = starting address as defined by as[15:8] on the rising edge of prgm . 2. register write data: dp[15:0]. 3. register write control: iostrb p ? (r/ w p) ? is p. some processors, including ti tms320lc54x, have three major memory spaces. program space ( ps signal); data space ( ds signal); and i/o space ( is signal). the trailblazers internal sram has two 32kb regions that are restricted to either ds or ps space. register 0 controls the decoding for the internal sram. registers 1 through 5 control the address decoding for the external devices on the secondary bus. for processors that have a15 as the msb, the three memory spaces are restricted to 64mb each. however, the registers do allow for programmable address ranges in 8kb blocks. for processors with a[21:16] as the msb, there is a 4mb maximum address space that can be partitioned by programming registers 1 to 5.
IS82C600 integrated silicon solution, inc. 1-800-379-4774 17 preliminary tb001-0b 01/20/99 issi ? electrical specifications absolute maximum ratings symbol parameters ratings units v cc supply voltage C0.4 to 4.1 v t stg storage temperature C65 to +150 c p t power dissipation 1.5 w i out dc output current (low) 20 ma note: 1. stresses above the absolute maximum ratings can cause permanent damage to the device. dc electrical characteristics (over operating range) symbol parameter test conditona min max units v oh output high voltage vcc = min., i oh = C4.0 ma 2.4 v v ol output low voltage vcc = min., i ol = 8.0 ma 0.4 v v ih input high voltage 2.2 vcc + 0.3 v v il input low voltage (1) 0.3 0.8 v i li input leakage gnd v in v cc C2 2 m a i lo output leakage gnd v out v cc , outputs disabled C2 2 m a note: 1. v il (min) = C2.0v for pulse width less than 10 m s. ac specification: 25 pf load internal sram cycles primary bus master -8 -9 -10 t# parameter min max min max min max units t1 data access time from rdp low 5 5.5 6 ns t2 data access time from address valid (5x cpu) 8 9 10 ns t3 data access time from address (54x cpu) 8 9 10 ns t4 data access time from ps/ds/is 8 9 10 ns t5 data access time from mstrbp 5 5.5 6 ns t6 data access time from csintp 6 6.5 7 ns t7 address to wep valid 1 1 1 ns t8 write data setup time before wep high 4 4 4 ns t9 write data hold time after wep high 0 0 0 ns t10 write data setup time before mstrb high 4 4 4 ns t11 write data hold time after mstrb high 0 0 0 ns operating range range ambient temperature vcc commercial 0 c to +70 c 3.0v to 3.6v industrial C40 c to +85 c 3.0v to 3.6v
18 integrated silicon solution, inc. 1-800-379-4774 preliminary tb001-0b 01/20/99 IS82C600 issi ? primary bus master local mode t# parameter min max min max min max units t12 mstrbp / iostrbp active to 0 5 0 5.5 0 6 ns oememp active delay t13 wep active to wmemp active delay 0 5 0 5.5 0 6 ns t14 mstrbp / iostrbp active to wememp delay 0 5 0 5.5 0 6 ns t15 psp / dsp / isp active to csmemp [5:0] delay 0 5 0 5.5 0 6 ns primary bus master remote mode (non- xcvr xcvr xcvr xcvr xcvr mode) t# parameter min max min max min max units t16 r/ w p, psp , dsp , isp , mstrbp , iostrbp , rdp , 0 5 0 5.5 0 6 ns wep delay to corresponding control signals on secondary bus t17 dp to ds write mode (r/ w =0) 0 5 0 5.5 0 6 ns t18 ds to dp read mode (r/ w =1) 0 5 0 5.5 0 6 ns t19 mstrbp / iostrbp active to oemems active delay 0 5 0 5.5 0 6 ns t20 wep active to wemems active delay 0 5 0 5.5 0 6 ns t21 mstrb / iostrbp active to wemems delay 0 5 0 5.5 0 6 ns t22 psp / dsp / isp active to csmems [5:0] delay 0 5 0 5.5 0 6 ns primary bus master xcvr xcvr xcvr xcvr xcvr mode t# parameter min max min max min max units t23 r/ w p, psp , dsp , isp , mstrbp , iostrbp , rdp ,030303ns wep delay to corresponding control signals on secondary bus t24 ds to dp delay (r/ w =high) read 0 5 0 5.5 0 6 ns from secondary bus t25 dp to ds delay (r/ w =0) write to secondary bus 0 5 0 5.5 0 6 ns note: 1. in the above list, the timing parameters are specified with the primary bus master as the basis.
IS82C600 integrated silicon solution, inc. 1-800-379-4774 19 preliminary tb001-0b 01/20/99 issi ? read cycle 1: primary bus internal sram read cycle timing (ti tms320lc5x/c5x dsp) clkout (from dsp) ap[15:0] csintp, psp, dsp, isp rdp dp[15:0] data valid address valid t2 t1 read cycle 2: primary bus internal sram read cycle timing (ti tms320lc54x/c54x dsp) clkout (from dsp) ap[15:0] csintp, psp, dsp, isp mstrbp r/wp = 1 dp[15:0] address valid t5 t4 t3 t6 data valid
20 integrated silicon solution, inc. 1-800-379-4774 preliminary tb001-0b 01/20/99 IS82C600 issi ? write cycle 1: primary bus internal sram write cycle timing (ti tms320lc5x/c5x dsp) write cycle 2: primary bus internal sram write cycle timing (ti tms320lc54x/c54x dsp) ap[15:0] wep dp[15:0] data valid address valid t7 t8 t9 clkout (from dsp) ap[15:0] mstrbp r/wp dp[15:0] address valid t10 t11 data valid note: 1. all timings are at zero wait state. however, external writes require two cycles to prevent external bus conflicts. (refer to the ti tms320lc54x/c54x databook.) note: 1. all timings are at zero wait state. however, external writes require two cycles to prevent external bus conflicts. (refer to the ti tms320lc54x/c54x databook.)
IS82C600 integrated silicon solution, inc. 1-800-379-4774 21 preliminary tb001-0b 01/20/99 issi ? primary bus control signals for oememp oememp oememp oememp oememp , wememp wememp wememp wememp wememp , and csmemp csmemp csmemp csmemp csmemp [5:0] primary bus to secondary bus delay note: 1. tx1 = timings from t12 through t15. mstrbp, iostrbp, wep, psp, dsp, isp oememp, wememp, csmemp tx1 mstrbp, iostrbp, r/wp, rdp, psp, dsp, isp wep, dp oememp, wememp, wemems, csmemp, ds tx2 note: 1. tx2 = timings from t16 through t25. ordering information commercial range: 0 c to +70 c speed (ns) order part number package 8 IS82C600-8b pbga 9 IS82C600-9b pbga 10 IS82C600-10b pbga ordering information industrial range: C40 c to +85 c speed (ns) order part number package 8 IS82C600-8bi pbga 9 IS82C600-9bi pbga 10 IS82C600-10bi pbga issi ? integrated silicon solution, inc. 2231 lawson lane santa clara, ca 95054 tel: 1-800-379-4774 fax: (408) 588-0806 e-mail: sales@issi.com www.issi.com

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